A low-dropout (LDO) regulator accepts an unregulated input voltage (VIN) and provides a regulated output voltage (VOUT) that is nearly independent of output current (e.g. a load current). A PMOS pass transistor is used to minimize the voltage difference between the input and output of a LDO regulator, and hence increases power conversion efficiency.
FIG. 1 shows the schematic of a typical LDO regulator according to the art, which consists of a pass transistor, an error amplifier, a reference voltage, a feedback resistor network and an optional output capacitor. Frequency compensation to achieve stability in a typical LDO is necessary as there are two high-impedance nodes, which are at the error amplifier output and at the drain of pass transistor. To provide such frequency compensation dominant-pole compensation and pole-zero cancellation are commonly used in the art, but these limit the choices of combinations of the output capacitance (COUT) and its equivalent-series-resistance (RESR) for LDO regulator stability. Furthermore, since the loop bandwidth of a conventional LDO is degraded by dominant-pole compensation, optimization between stability and transient response is difficult to achieve.